1. Field of the Invention
The present invention is directed to the design of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of selecting buffer delays for a clock tree in an integrated circuit design.
2. Description of Related Art
As integrated circuit designs incorporate greater numbers of transistors and larger interconnect delays, timing closure becomes an increasingly important step in the design cycle. One of the techniques used to achieve timing closure is the insertion of buffers in tree structures of the integrated circuit design, for example, to improve signal integrity, to reduce interconnect delay, and to split driver loading.